 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| FAN7392 -- High-Current, High- and Low-Side, Gate-Drive IC July 2009 FAN7392 High-Current, High- and Low-Side, Gate-Drive IC Features Floating Channel for Bootstrap Operation to +600V 3A/3A Sourcing/Sinking Current Driving Capability Common-Mode dv/dt Noise Canceling Circuit 3.3V Logic Compatible Separate Logic Supply (VDD) Range from 3.3V to 20V Under-Voltage Lockout for VCC and VBS Cycle-by-Cycle Edge-Triggered Shutdown Logic Matched Propagation Delay for Both Channels Outputs In-phase with Input Signals Available in 14-DIP and 16-SOP (Wide) Packages Description The FAN7392 is a monolithic high- and low-side gate drive IC, that can drive high-speed MOSFETs and IGBTs that operate up to +600V. It has a buffered output stage with all NMOS transistors designed for high pulse current driving capability and minimum cross-conduction. Fairchild's high-voltage process and common-mode noise canceling techniques provide stable operation of the high-side driver under high dv/dt noise circumstances. An advanced level-shift circuit offers high-side gate driver operation up to VS=-9.8V (typical) for VBS=15V. Logic inputs are compatible with standard CMOS or LSTTL output, down to 3.3V logic. The UVLO circuit prevents malfunction when VCC and VBS are lower than the specified threshold voltage. The high-current and low-output voltage drop feature makes this device suitable for halfand full-bridge inverters, like switching-mode power supply and high-power DC-DC converter applications. Applications High-Speed Power MOSFET and IGBT Gate Driver Server Power Supply Uninterrupted Power Supply (UPS) Telecom System Power Supply Distributed Power Supply Motor Drive Inverter 14-PDIP 16-SOP Ordering Information Part Number FAN7392N FAN7392M FAN7392MX -40C to +125C Operating Temperature Range Package 14-PDIP 16-SOP Eco Status Packing Method Tube RoHS Tube Tape and Reel For Fairchild's definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. (c) 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.2 www.fairchildsemi.com FAN7392 -- High-Current, High- and Low-Side, Gate-Drive IC Typical Application Diagrams Up to 600V 15V 8 Q1 NC VDD HIN SD LIN VSS NC HO VB VS NC VCC COM LO R1 7 9 6 CBOOT HIN 10 5 Load DBOOT RBOOT Controller SD LIN 11 4 12 3 15V C1 13 2 Q2 R2 14 1 Figure 1. Typical Application Circuit (Referenced 14-DIP) Up to 600V Q1 9 15V 10 NC NC VDD HIN SD LIN VSS NC HO VB VS NC NC VCC COM LO R1 8 7 CBOOT 11 6 Load DBOOT HIN 12 5 Controller SD LIN 13 4 RBOOT 14 3 15V C1 15 2 Q2 R2 16 1 Figure 2. Typical Application Circuit (Referenced 16-SOP) (c) 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.2 www.fairchildsemi.com 2 FAN7392 -- High-Current, High- and Low-Side, Gate-Drive IC Internal Block Diagram 6 UVLO VB DRIVER VDD 9 PULSE GENERATOR NOISE CANCELLER R S R Q 7 HO HIN 10 SCHMITT TRIGGER INPUT 5 HS(ON/OFF) VS LIN 12 UVLO 3 DRIVER VCC SD 11 CYCLE-By-CYCLE EDGE TRIGGERED SHUTDOWN LS(ON/OFF) VSS/COM LEVEL SHIFT DELAY 1 LO VSS 13 Pin 4, 8, and 14 are no connection 2 COM Figure 3. Functional Block Diagram (Referenced 14-Pin) 7 UVLO VB DRIVER VDD 11 PULSE GENERATOR NOISE CANCELLER R S R Q 8 HO HIN 12 SCHMITT TRIGGER INPUT 6 HS(ON/OFF) VS LIN 14 UVLO 3 DRIVER VCC SD 13 CYCLE-By-CYCLE EDGE TRIGGERED SHUTDOWN LS(ON/OFF) VSS/COM LEVEL SHIFT DELAY 1 LO VSS 15 Pin 4, 5, 9,10 and 16 are no connection 2 COM Figure 4. Functional Block Diagram (Referenced 16-SOP) (c) 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.2 www.fairchildsemi.com 3 FAN7392 -- High-Current, High- and Low-Side, Gate-Drive IC Pin Configuration LO COM VCC NC NC VS VB HO 1 16 NC VSS LIN SD HIN VDD NC NC LO COM VCC NC VS VB HO 1 14 NC VSS LIN SD HIN VDD NC 2 15 FAN7392M 2 13 3 14 FAN7392 (a) 14-DIP 3 12 4 13 4 11 5 12 5 10 6 11 6 9 7 10 7 8 8 9 (b) 16-SOP (Wide Body) Figure 5. Pin Configurations (Top View) Pin Definitions 14-Pin 1 2 3 5 6 7 9 10 11 12 13 4,8,14 16-Pin 1 2 3 6 7 8 11 12 13 14 15 4, 5, 9, 10, 16 Name LO COM VCC VS VB HO VDD HIN SD LIN VSS NC Low-Side Return Description Low-Side Driver Output Low-Side Supply Voltage High-Voltage Floating Supply Return High-Side Floating Supply High-Side Driver Output Logic Supply Voltage Logic Input for High-Side Gate Driver Output Logic Input for Shutdown Function Logic Input for Low-Side Gate Driver Output Logic Ground No Connect (c) 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.2 www.fairchildsemi.com 4 FAN7392 -- High-Current, High- and Low-Side, Gate-Drive IC Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA=25C unless otherwise specified. Symbol VB VS VHO VCC VLO VDD VSS VIN dVS/dt PD JA TJ TSTG Characteristics High-Side Floating Supply Voltage High-Side Floating Offset Voltage High-Side Floating Output Voltage Low-Side Supply Voltage Low-Side Floating Output Voltage Logic Supply Voltage Logic Supply Offset Voltage Logic Input Voltage (HIN, LIN and SD) Allowable Offset Voltage Slew Rate Power Dissipation(1, 2, 3) Thermal Resistance Maximum Junction Temperature Storage Temperature 14-PDIP 16-SOP 14-PDIP 16-SOP Min. -0.3 VB-25.0 VS-0.3 -0.3 -0.3 -0.3 VCC-25.0 VSS-0.3 Max. 625.0 VB+0.3 VB+0.3 25.0 VCC+0.3 VSS+25.0 VCC+0.3 VDD+0.3 50 1.6 1.3 75 95 +150 Unit V V V V V V V V V/ns W C/W C C -55 +150 Notes: 1. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material). 2. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions, natural convection; and JESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages. 3. Do not exceed power dissipation (PD) under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VB VS VHO VCC VLO VDD VSS VIN TA Parameter High-Side Floating Supply Voltage High-Side Floating Supply Offset Voltage High-Side Output Voltage Low-Side Supply Voltage Low-Side Output Voltage Logic Supply Voltage Logic Supply Offset Voltage Logic Input Voltage Operating Ambient Temperature Min. VS+10 6-VCC VS 10 0 VSS+3 -5 VSS -40 Max. VS+20 600 VB 20 VCC VSS+20 5 VDD +125 Unit V V V V V V V V C (c) 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.2 www.fairchildsemi.com 5 FAN7392 -- High-Current, High- and Low-Side, Gate-Drive IC Electrical Characteristics VBIAS(VCC, VBS, VDD)=15.0V, VSS=COM=0V and TA=25C, unless otherwise specified. The VIH, VIL, and IIN parameters are referenced to VSS and are applicable to the respective input leads: HIN, LIN, and SD. The VO and IO parameters are referenced to VS and COM and are applicable to the respective output leads: HO and LO. Symbol IQCC IQDD IPCC IPDD ISD VCCUV+ VCCUVVCCUVH Characteristics Quiescent VCC Supply Current Quiescent VDD Supply Current Operating VCC Supply Current Operating VDD Supply Current Shutdown Supply Current VCC Supply Under-Voltage Positive-Going Threshold Voltage VCC Supply Under-Voltage Negative-Going Threshold Voltage VCC Supply Under-Voltage Lockout Hysteresis Voltage Test Condition VIN=0V or VDD VIN=0V or VDD fIN=20kHz, rms, VIN=15VPP fIN=20kHz, rms, VIN=15VPP SD=VDD VIN=0V, VCC=Sweep VIN=0V, VCC=Sweep VIN=0V, VCC=Sweep Min. Typ. Max. Unit 40 80 10 430 300 120 7.7 7.3 8.8 8.4 0.4 9.9 9.5 A A A A A V V V Low-Side Power Supply Section Bootstrapped Supply Section IQBS IPBS VBSUV+ VBSUVVBSUVH ILK Quiescent VBS Supply Current Operating VBS Supply Current VBS Supply Under-Voltage Positive-Going Threshold Voltage VBS Supply Under-Voltage Negative-Going Threshold Voltage VBS Supply Under-Voltage Lockout Hysteresis Voltage Offset Supply Leakage Current VIN=0V or VDD fIN=20kHz, rms value VIN=0V, VBS=Sweep VIN=0V, VBS=Sweep VIN=0V, VBS=Sweep VB=VS=600V VDD=3V VDD=15V VDD=3V VDD=15V VIN=VDD VIN=0V 375 No Load (IO=0A) No Load (IO=0A) VO=0V, PW 10s VO=15V, PW 10s 2.5 2.5 -5.0 -9.8 3.0 3.0 5.0 -7.0 Current(4) 750 20 2.4 9.5 0.8 6.0 40 3 7.7 7.3 60 500 8.8 8.4 0.4 50 9.9 9.5 130 A A V V V A Input Locic Section (HIN, LIN, and SD) VIH Logic "1" Input Threshold Voltage V V V V A A K VIL IIN+ IINRIN VOH VOL IO+ IO- Logic "0" Input Threshold Voltage Logic Input High Bias Current Logic Input Low Bias Current Logic Input Pull-Down Resistance Gate Driver Output Section High-Level Output Voltage (VBIAS - VO) Low-Level Output Voltage Output High, Short-Circuit Pulsed Current(4) Output Low, Short-Circuit Pulsed 1.5 200 V mV A A V V VSS/COM VSS-COM/COM-VSS Voltage Educability - VS Allowable Negative VS Pin Voltage for HIN Signal Propagation to HO (c) 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.2 www.fairchildsemi.com 6 FAN7392 -- High-Current, High- and Low-Side, Gate-Drive IC Dynamic Electrical Characteristics VBIAS(VCC, VBS, VDD)=15.0V, VSS=COM=0V, CLOAD=1000pF, TA=25C, unless otherwise specified. Symbol ton toff tsd tr tf MT Parameter Turn-On Propagation Delay Time Turn-Off Propagation Delay Time Shutdown propagation Delay Time(4) Turn-On Rise Time Turn-Off Fall Time Delay Matching, HO & LO Turn-On/Off VS=0V VS=0V Conditions Min. Typ. 130 150 130 25 20 Max. 180 200 180 50 45 35 Unit ns ns ns ns ns ns Note: 4. These parameters guaranteed by design. (c) 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.2 www.fairchildsemi.com 7 FAN7392 -- High-Current, High- and Low-Side, Gate-Drive IC Typical Characteristics 180 200 160 180 tON [ns] 140 tOFF [ns] -20 0 20 40 60 80 100 120 160 120 140 100 120 80 -40 100 -40 -20 0 20 40 60 80 100 120 Temperature [C] Temperature [C] Figure 6. Turn-On Propagation Delay vs. Temperature Figure 7. Turn-Off Propagation Delay vs. Temperature 50 50 40 40 tR [ns] 30 tF [ns] -20 0 20 40 60 80 100 120 30 20 20 10 10 0 -40 0 -40 -20 0 20 40 60 80 100 120 Temperature [C] Temperature [C] Figure 8. Turn-On Rise Time vs. Temperature Figure 9. Turn-Off Fall Time vs. Temperature 30 30 MTON [ns] 20 MTOFF [ns] -20 0 20 40 60 80 100 120 20 10 10 0 -40 0 -40 -20 0 20 40 60 80 100 120 Temperature [C] Temperature [C] Figure 10. Turn-On Delay Matching vs. Temperature Figure 11. Turn-Off Delay Matching vs. Temperature (c) 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.2 www.fairchildsemi.com 8 FAN7392 -- High-Current, High- and Low-Side, Gate-Drive IC Typical Characteristics (Continued) 180 40 160 30 140 IIN+ [A] -20 0 20 40 60 80 100 120 tSD [ns] 20 120 100 10 80 -40 0 -40 -20 0 20 40 60 80 100 120 Temperature [C] Temperature [C] Figure 12. Shutdown Propagation Delay vs. Temperature Figure 13. Logic Input High Bias Current vs. Temperature 80 70 60 120 100 IQCC [A] 50 40 30 20 10 0 -40 -20 0 20 40 60 80 100 120 IQBS [A] 80 60 40 20 0 -40 -20 0 20 40 60 80 100 120 Temperature [C] Temperature [C] Figure 14. Quiescent VCC Supply Current vs. Temperature Figure 15. Quiescent VBS Supply Current vs. Temperature 1000 1000 800 800 IPBS [A] IPCC [A] 600 600 400 400 200 200 0 -40 -20 0 20 40 60 80 100 120 0 -40 -20 0 20 40 60 80 100 120 Temperature [C] Temperature [C] Figure 16. Operating VCC Supply Current vs. Temperature Figure 17. Operating VBS Supply Current vs. Temperature (c) 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.2 www.fairchildsemi.com 9 FAN7392 -- High-Current, High- and Low-Side, Gate-Drive IC Typical Characteristics (Continued) 9.5 9.5 9.0 VCCUV+ [V] 9.0 VCCUV- [V] 8.5 8.5 8.0 8.0 7.5 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 -40 Temperature [C] Temperature [C] Figure 18. VCC UVLO+ vs. Temperature Figure 19. VCC UVLO- vs. Temperature 9.5 9.5 9.0 VBSUV+ [V] 9.0 VBSUV- [V] 8.5 8.5 8.0 8.0 7.5 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 -40 Temperature [C] Temperature [C] Figure 20. VBS UVLO+ vs. Temperature Figure 21. VBS UVLO- vs. Temperature 1.5 20 15 10 VOL [mV] -20 0 20 40 60 80 100 120 1.0 VOH [V] 5 0 -5 -10 -15 0.5 0.0 -40 -20 -40 -20 0 20 40 60 80 100 120 Temperature [C] Temperature [C] Figure 22. High-Level Output Voltage vs. Temperature Figure 23. Low-Level Output Voltage vs. Temperature (c) 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.2 www.fairchildsemi.com 10 FAN7392 -- High-Current, High- and Low-Side, Gate-Drive IC Typical Characteristics (Continued) 11 10 9 10 8 VIH [V] VIL [V] 9 7 6 5 8 7 4 3 -40 6 -40 -20 0 20 40 60 80 100 120 -20 0 20 40 60 80 100 120 Temperature [C] Temperature [C] Figure 24. Logic High Input Voltage vs. Temperature Figure 25. Logic Low Input Voltage vs. Temperature -7 12 Logic Threshold Voltage [V] -8 10 8 6 4 2 0 0 2 4 6 8 10 12 14 16 18 20 VS [V] -9 -10 -11 VIH VIL -12 -40 -20 0 20 40 60 80 100 120 Temperature [C] VDD Logic Supply Voltage [V] Figure 26. Allowable Negative VS Voltage vs. Temperature Figure 27. Input Logic (HIN & LIN) Threshold Voltage vs. VDD Supply Voltage . -4 -6 VCC=VBS COM=0V TA=25C VS [V] -8 -10 -12 -14 -16 10 11 12 13 14 15 16 17 18 19 20 Supply Voltage [V] Figure 28. Allowable Negative Vs Voltage for HIN Signal Propagation to High Side vs. Supply Voltage (c) 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.2 www.fairchildsemi.com 11 FAN7392 -- High-Current, High- and Low-Side, Gate-Drive IC Switching Time Definitions 15V 8 NC VDD HIN SD LIN VSS NC HO VB VS NC VCC COM LO 7 HO 9 6 1nF 10F 100nF (0 to 600V) 10F 15V HIN SD LIN 10 5 11 4 15V 12 3 10F 13 2 100nF 14 1 LO 1nF Figure 29. Switching Time Test Circuit (Referenced 14-DIP) HIN LIN SD HO LO Shutdown Skip Figure 30. Input/Output Timing Diagram HIN LIN 50% 50% tON tR 90% tOFF 90% tF HO LO 10% 10% Figure 31. Switching Time Waveform Definitions (c) 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.2 www.fairchildsemi.com 12 FAN7392 -- High-Current, High- and Low-Side, Gate-Drive IC Switching Time Definitions (Continued) 50% SD tSD 90% HO LO Figure 32. Shutdown Waveform Definition HIN LIN 50% 50% LO 10% HO 10% 90% MT 90% MT LO HO Figure 33. Delay Matching Waveform Definitions (c) 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.2 www.fairchildsemi.com 13 FAN7392 -- High-Current, High- and Low-Side, Gate-Drive IC Application Information Negative VS Transient The bootstrap circuit has the advantage of being simple and low cost, but has some limitations. The biggest difficulty with this circuit is the negative voltage present at the emitter of the high-side switching device when highside switch is turned-off in half-bridge application. If the high-side switch, Q1, turns-off while the load current is flowing to an inductive load, a current commutation occurs from high-side switch, Q1, to the diode, D2, in parallel with the low-side switch of the same inverter leg. Then the negative voltage present at the emitter of the high-side switching device, just before the freewheeling diode, D2, starts clamping, causes load current to suddenly flow to the low-side freewheeling diode, D2, as shown in Figure 34. DC+ Bus Q1 D1 iLOAD ifreewheeling Figure 36 and Figure 37 show the commutation of the load current between high-side switch, Q1, and low-side freewheelling diode, D3, in same inverter leg. The parasitic inductances in the inverter circuit from the die wire bonding to the PCB tracks are jumped together in LC and LE for each IGBT. When the high-side switch, Q1, and low-side switch, Q4, are turned on, the VS1 node is below DC+ voltage by the voltage drops associated with the power switch and the parasitic inductances of the circuit due to load current is flows from Q1 and Q4, as shown in Figure 36. When the high-side switch, Q1, is turned off and Q4, remained turned on, the load current to flows the low-side freewheeling diode, D3, due to the inductive load connected to VS1 as shown in Figure 37. The current flows from ground (which is connected to the COM pin of the gate driver) to the load and the negative voltage present at the emitter of the high-side switching device. In this case, the COM pin of the gate driver is at a higher potential than the VS pin due to the voltage drops associated with freewheeling diode, D3, and parasitic elements, LC3 and LE3. DC+ Bus VS Load Q2 D2 LC1 VLC1 LC2 Q2 Q1 D1 iLOAD LE1 VLE1 D2 ifreewheeling LE2 VS2 VLC4 Figure 34. Half-Bridge Application Circuits This negative voltage can be trouble for the gate driver's output stage, there is the possibility to develop an overvoltage condition of the bootstrap capacitor, input signal missing and latch-up problems because it directly affects the source VS pin of the gate driver, as shown in Figure 35. This undershoot voltage is called "negative VS transient". VS1 LC3 Load LC4 Q4 Q3 D3 D4 LE3 VLE4 LE4 Figure 36. Q1 and Q4 Turn-On Q1 GND LC1 DC+ Bus LC2 Q2 D1 iLOAD ifreewheeling D2 Q1 VS GND Freewheeling LE1 LE2 VS2 VLC4 VS1 LC3 VLC3 Load LC4 Q4 Q3 D3 D4 LE3 VLE3 VLE4 LE4 Figure 35. VS Waveforms During Q1 Turn-Off Figure 37. Q1 Turn-Off and D3 Conducting (c) 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.2 www.fairchildsemi.com 14 FAN7392 -- High-Current, High- and Low-Side, Gate-Drive IC Placement of Components The FAN7392 has a negative VS transient performance curve, as shown in Figure 38. The recommended placement and selection of component as follows: Place a bypass capacitor between the VDD and VSS pins. A ceramic 1F capacitor is suitable for most applications. This component should be placed as close as possible to the pins to reduce parasitic elements. The bypass capacitor from VCC to COM supports both the low-side driver and bootstrap capacitor recharge. A value at least ten times higher than the bootstrap capacitor is recommended. The bootstrap resistor, RBOOT, must be considered in sizing the bootstrap resistance and the current developed during initial bootstrap charge. If the resistor is needed in series with the bootstrap diode, verify that VB does not fall below COM (ground). Recommended use is typically 5 ~ 10 that increase the VBS time constant. If the votage drop of of bootstrap resistor and diode is too high or the circuit topology does not allow a sufficient charging time, a fast recovery or ultra-fast recovery diode can be used. The bootstrap capacitor, CBOOT, uses a low-ESR capacitor, such as ceramic capacitor. It is stongly recommended that the placement of components is as follows: Place components tied to the floating voltage pins (VB and VS) near the respective high-voltage portions of the device and the FAN7392. NC (not connected) pins in this package maximize the distance between the high-voltage and low-voltage pins (see Figure 5). Place and route for bypass capacitors and gate resistors as close as possible to gate drive IC. Locate the bootstrap diode, DBOOT, as close as possible to bootstrap capacitor, CBOOT. The bootstrap diode must use a lower forward voltage drop and minimal switching time as soon as possible for fast recovery or ultra-fast diode. -100 -90 -80 -70 -60 VS [V] -50 -40 -30 -20 -10 0 0 100 200 300 400 500 600 700 800 900 1000 Pulse Width [ns] Figure 38. Negative VS Transient Chracteristic Even though the FAN7392 has been shown able to handle these negative VS tranient conditions, it is strongly recommended that the circuit designer limit the negative VS transient as much as possible by careful PCB layout to minimized the value of parasitic elements and component use. The amplitude of negative VS voltage is proportional to the parasitic inductances and the turn-off speed, di/dt, of the switching device. General Guidelines Printed Circuit Board Layout The relayout recommended for minimized parasitic elements is as follows: Direct tracks between switches with no loops or deviation. Avoid interconnect links. These can add significant inductance. Reduce the effect of lead-inductance by lowering package height above the PCB. Consider co-locating both power switches to reduce track length. To minimize noise coupling, the ground plane should not be placed under or near the high-voltage floating side. To reduce the EM coupling and improve the power switch turn-on/off performance, the gate drive loops must be reduced as much as possible. (c) 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.2 www.fairchildsemi.com 15 FAN7392 -- High-Current, High- and Low-Side, Gate-Drive IC Physical Dimensions . 14 19.56 18.80 8 6.60 6.09 1 7 (1.74) 3.56 3.30 1.77 1.14 5.33 MAX 0.38 MIN 8.12 7.62 0.35 0.20 3.81 3.17 0.58 0.35 2.54 8.82 NOTES: UNLESS OTHERWISE SPECIFIED THIS PACKAGE CONFORMS TO A) JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS ARE EXCLUSIVE OF BURRS, C) MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5-1994 E) DRAWING FILE NAME: MKT-N14AREV7 Figure 39. 14-Lead Dual In-Line Package (DIP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. (c) 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.2 www.fairchildsemi.com 16 FAN7392 -- High-Current, High- and Low-Side, Gate-Drive IC Physical Dimensions (Continued) . 10.300.20 8.890 16 B 9 A 9.44 7.500.10 10.325 9.2 10.95 1 PIN ONE INDICATOR 0.51 0.35 0.25 8 1.27 M 1.75 TYP 0.55 TYP 1.27 TYP LAND PATTERN RECOMMENDATION CBA 2.65 MAX SEE DETAIL A C 0.10 C 0.200.10 SEATING PLANE 0.33 0.20 0.75 0.25 X 45 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-013, ISSUE E, DATED SEPT 2005. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. pdip8_dim.pdf D) LANDPATTERN STANDARD: SOIC127P1030X265-16L E) DRAWING FILENAME: MKT-16Brev2 (R0.10) GAGE PLANE (R0.10) 8 0 0.25 0.40~1.27 (1.40) SEATING PLANE DETAIL A SCALE: 2:1 M16BREV2 Figure 40. 16-Lead Small Outline Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. (c) 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.2 www.fairchildsemi.com 17 FAN7392 -- High-Current, High- and Low-Side, Gate-Drive IC (c) 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.2 www.fairchildsemi.com 18 |
Price & Availability of FAN7392
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |